Multi-master multi-slave system bus in a field programmable gate array (FPGA)
US6483342B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2001 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | May 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/081
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An embedded system bus is woven between a plurality of embedded master elements and at least one slave element within the FPGA device, and provides an external processor interface allowing direct access to any of the plurality of embedded slave elements. Using the embedded system bus, any of a plurality of masters may be allowed to program an embedded element, e.g., embedded FPGA logic, whereas conventional FPGAs allowed only a single master (e.g., a processor) to program the embedded FPGA logic. The embedded system bus is a group of signals, typically data, address and control, that connects system elements together and provides a basic protocol for the flow of data. The embedded system bus allows for control, configuration and status determination of the FPGA device. The embedded system bus is preferably a dedicated function available at all times for arbitrated access to allow communication between the various embedded system components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.