Input circuit having signature circuits in parallel in semiconductor device
US6483373B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2000 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | Jan 24, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An input circuit having one or more individual signature circuits connected in parallel between an input line and an voltage node in a semiconductor device and an individual signature circuit are provided. The individual signature circuits are isolated from an input/output port to which a high frequency signal is applied so that the input/output port of the semiconductor device can operate at high speed. The signature circuits are provided for an input/output port to which a relatively low frequency signal is applied. An individual signature circuit includes an indexer and a selector connected in series between the voltage node and the input line. The selector includes two terminals which are electrically short-circuited or snapped in response to a control signal, and the indexer includes one or more voltage reducing devices connected in series between input and output terminals of the indexer and signature fuses each of which is connected in parallel to corresponding one of the voltage reducing devices. Voltage drop in the indexer varies with a combination of the signature fuses which are cut or uncut. By varying a voltage drop of an indexer in each of the individual signature cir…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.