System and method for reducing timing mismatch in sample and hold circuits using an FFT and decimation
US6483448B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2001 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | Jun 22, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to modify a hold signal for one or more of the plurality of sample and hold subcircuits to thereby reduce timing mismatch between the plurality of sample and hold subcircuits and distortion associated therewith. The present invention also comprises a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit. The method comprises detecting timing mismatch associated with a plurality of sample and hold subcircuits and modifying a hold signal for one or more of the subcircuits. In one exemplary method, the timing mismatch is detected by converting the sample and hold circuit output data to digital data and performing a fast Fourier transform thereon, and analyzing the resulting energy spectrum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.