Method and apparatus for overlapping programmable address regions
US6484227B1 · kind B1 · utility
13Cited by
1References
19Claims
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Key dates
| Filing date | Aug 23, 1999 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | Aug 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/652
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flexible address mapping method and mechanism allows mapping regions of a microcontroller's memory and I/O address spaces for a variety of applications by defining memory regions which are mapped to one of a set of physical devices by a programmable address mapper controlled by a set of programmable address registers. The mapping allows setting attributes for a memory region to prohibit writes, caching, and code execution. A deterministic priority scheme allows memory regions to overlap, mapping addresses in overlapping regions to the device specified by the highest priority programmable address register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.