Patent · US Expired

Method of producing phase masks in an automated layout generation for integrated circuits

US6485871B1 · kind B1 · utility

5Cited by

2References

11Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thomas Krüger · Leverkusen, DE
Werner Schiele · Ludwigsburg, DE

Key dates

Filing date	Oct 2, 2000
Grant date	Nov 26, 2002
Priority date	—
Expiry date	Oct 31, 2020

Classification

Technology area (CPC G)Physics
CPC primaryG03F1/26
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method of producing phase masks for automatically generating a layout for an integrated circuit includes the step of compacting a layout of an integrated circuit by processing a distance graph. A respective phase is allocated to at least some of a plurality of polygons in the layout in order to generate a phase mask, wherein the allocating step is performed during the processing of the distance graph.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.