Deep trench isolation for reducing soft errors in integrated circuits
US6486525B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 13, 1999 |
| Grant date | Nov 26, 2002 |
| Priority date | — |
| Expiry date | Jul 13, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having improved soft error protection and a method improving the soft error protection of an integrated circuit are disclosed. The integrated circuit comprises a substrate 72, a transistor formed in the substrate 72, a first region 74 (e.g. a well) formed in the substrate having a first conductivity type, a second region 84 below the first region 74 having a second conductivity type, and a trench formed in the substrate having a depth at least substantially as deep as the well. The trench 70 is filled with a non-conductive material 71 that forms a frame around the transistor, whereby soft errors due to electron-hole pairs caused by ionizing radiation in the frame are substantially eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.