Domino logic with low-threshold NMOS pull-up
US6486706B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2000 |
| Grant date | Nov 26, 2002 |
| Priority date | — |
| Expiry date | Dec 6, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A domino logic circuit includes an n-channel clock transistor coupled between a dynamic output node and a high voltage connection, the gate of the clock transistor further coupled to receive an inverse clock signal. A first inverter has an input connected to the dynamic output node. A second inverter with an input connected to the dynamic output node comprises a static CMOS circuit stage, the output of which is the output of the domino logic circuit. A p-channel level keeper transistor is connected between the dynamic output node and the high voltage connection, and the gate of the level keeper transistor is connected to the output of the first inverter. A pull-down circuit is connected between the dynamic output node and a low-voltage connection. A pull-up circuit is connected between the static CMOS circuit output and the high voltage connection. An output predischarge transistor is connected between the output of the static CMOS circuit and the low voltage connection, and is coupled to and controlled by a clock signal at its gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.