Overlay alignment measurement mark
US6486954B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2000 |
| Grant date | Nov 26, 2002 |
| Priority date | — |
| Expiry date | Feb 5, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01B11/002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An alignment mark comprising a first test zone and a second test zone for measuring the relative position between different layers of a semiconductor device. The alignment mark is used to determine the overlay error between layers of a semiconductor wafer while minimizing measurement inaccuracies caused by semiconductor manufacturing processes. The first test zone includes two sections, one in which test structures are formed on one layer and a second in which test structures are formed on a second layer. Each of these test structures is composed of smaller sub-structures. The second test zone includes two similar sections that are also composed of smaller sub-structures. The first and second test zones are configured so that the section of each test zone formed one layer is adjacent to the section of the other test zone that is formed on the other layer. By forming each of the periodic structures with smaller sized sub-structures, a more accurate measurement of any alignment error may be obtained. Another aspect of the present invention pertains to a method of utilizing the alignment mark so that an overlay measurement may be obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.