Memory module having buffer for isolating stacked memory devices
US6487102B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2000 |
| Grant date | Nov 26, 2002 |
| Priority date | — |
| Expiry date | Sep 18, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention utilizes a buffer to isolate a stack of memory devices, thereby taking advantage of the increased memory density available from stacked memory devices while reducing capacitive loading. A memory module in accordance with the present invention may include a stack of memory devices and a buffer coupled to the first and second memory devices and arranged to capacitively isolate the first and second memory devices from a bus. In a memory system in accordance with the present invention, multiple buffered stacks of memory devices are preferably coupled in a point-to-point arrangement, thereby further reducing capacitive loading.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.