Shared buffer memory architecture for asynchronous transfer mode switching and multiplexing technology
US6487207B1 · kind B1 · utility
14Cited by
57References
33Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 6, 1999 |
| Grant date | Nov 26, 2002 |
| Priority date | — |
| Expiry date | Dec 6, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An ATM switch including a multi-port memory is described. The multi-port memory having a dynamic random access memory (DRAM) and a plurality of input and output serial access memories (SAMs). Efficient, flexible transfer circuits and methods are described for transferring ATM data between the SAMs and the DRAM. The transfer circuits and methods include helper flip/flops to latch ATM data for editing prior to storage in the DRAM. Editing of ATM data transferred from the DRAM is also described. Dynamic parity generation and checking is described to detect errors induced during switching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.