Method and apparatus for denormal load handling
US6487653B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 1999 |
| Grant date | Nov 26, 2002 |
| Priority date | — |
| Expiry date | Aug 25, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49905
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor configured to dynamically switch its floating point load pipeline length from one stage in length to more than one stage in length is disclosed. The microprocessor may perform normal loads and detect denormal loads in a single clock cycle. The microprocessor temporarily stores each scheduled floating point instruction in a reissue buffer for at least one clock cycle. When a denormal load instruction is detected, the microprocessor is configured to add one or more stages to the floating point load pipeline to allow the denormal value to complete the conversion to an internal format. The longer pipeline is then used for all loads that follow the denormal load until there is an idle clock cycle or an abort occurs. At that point, the pipeline reverts back to its original shorter state. In addition, the microprocessor may be configured to cancel instructions scheduled assuming the denormal load would take only one clock cycle to complete. The canceled instruction is then “replayed” during a later clock cycle from the reissue buffer. A method for performing denormal loads and a computer system are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.