Method of controlling external models in system-on-chip verification
US6487699B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2000 |
| Grant date | Nov 26, 2002 |
| Priority date | — |
| Expiry date | Jan 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system and media for communicating with and controlling design logic modules (“cores”) which are external to a system-on-chip (“SOC”) design during verification of the design. An external memory-mapped test device (“EMMTD”) is coupled between a SOC design being tested in simulation, and cores external to the SOC design. Internal logic in the EMMTD provides for control and status monitoring of an external core coupled to an EMMTD bi-directional bus by enabling functions including driving data on the bus, reading the current state of data on the bus, and capturing positive and negative edge transitions on the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.