Robert J. Devins
25Patents
10h-index
20Co-inventors
71Inventor score
Filing activity: Sep 25, 1995 → Aug 14, 2008
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6571373B1 | Simulator-independent system-on-chip verification methodology | Physics | 95 | Expired |
| US6658633B2 | Automated system-on-chip integrated circuit design verification system | Physics | 85 | Expired |
| US6615167B1 | Processor-independent system-on-chip verification for embedded processor systems | Physics | 75 | Expired |
| US6539522B1 | Method of developing re-usable software for efficient verification of system-on-chip integrated circuit designs | Physics | 47 | Expired |
| US5784595A | DMA emulation for non-DMA capable interface cards | Physics | 47 | Expired |
| US6427224B1 | Method for efficient verification of system-on-chip integrated circuit designs including an embedded processor | Physics | 34 | Expired |
| US6952215B1 | Method and system for graphics rendering using captured graphics hardware instructions | Physics | 25 | Expired |
| US6487699B1 | Method of controlling external models in system-on-chip verification | Physics | 17 | Expired |
| US6762761B2 | Method and system for graphics rendering using hardware-event-triggered execution of captured graphics hardware instructions | Physics | 14 | Expired |
| US5668957A | Method and apparatus for providing virtual DMA capability on an adapter connected to a computer system bus with no DMA support | Physics | 12 | Expired |
| US7849362B2 | Method and system of coherent design verification of inter-cluster interactions | Physics | 10 | Active |
| US6525738B1 | Display list processor for decoupling graphics subsystem operations from a host processor | Physics | 10 | Expired |
| US6865502B2 | Method and system for logic verification using mirror interface | Physics | 9 | Expired |
| US6868545B1 | Method for re-using system-on-chip verification software in an operating system | Physics | 6 | Expired |
| US7353131B2 | Method and system for logic verification using mirror interface | Physics | 4 | Expired |
| US7451070B2 | Optimal bus operation performance in a logic simulation environment | Physics | 4 | Active |
| US8234624B2 | System and method for developing embedded software in-situ | Physics | 3 | Active |
| US5768631A | Audio adapter card and method for trapping audio command and producing sound corresponding to the trapped command | Physics | 3 | Expired |
| US7729877B2 | Method and system for logic verification using mirror interface | Physics | 2 | Active |
| US7711534B2 | Method and system of design verification | Physics | 2 | Active |
| US7353156B2 | Method of switching external models in an automated system-on-chip integrated circuit design verification system | Physics | 2 | Expired |
| US7917348B2 | Method of switching external models in an automated system-on-chip integrated circuit design verification system | Physics | 1 | Active |
| US9367493B2 | Method and system of communicating between peer processors in SoC environment | Physics | 1 | Active |
| US7176927B2 | Method and system for graphics rendering using hardware-event-triggered execution of captured graphics hardware instructions | Physics | 0 | Expired |
| US8140314B2 | Optimal bus operation performance in a logic simulation environment | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.