Dynamic code motion optimization and path tracing
US6487715B1 · kind B1 · utility
36Cited by
13References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 16, 1999 |
| Grant date | Nov 26, 2002 |
| Priority date | — |
| Expiry date | Apr 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of reordering instructions. Barrier instructions are determined. The method determines when a processor stall may occur, and hoists subsequent instructions to fill in the stall time. However, instructions are not hoisted above the barrier instructions. Barrier instructions include branch instructions, store and load instructions, and instructions which, if hoisted, cause the number of available registers to be exceeded. The method produces a reordered instruction trace and statistics regarding the effectiveness of the reordering.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.