Method relating to a polishing system having a multi-phase polishing layer
US6488570B1 · kind B1 · utility
45Cited by
15References
8Claims
0Family size
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Key dates
| Filing date | Sep 20, 2000 |
| Grant date | Dec 3, 2002 |
| Priority date | — |
| Expiry date | Sep 20, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B23/0021
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
A method of making a polishing pad composition comprising a high modulus phase component and a low modulus phase component, and a method of polishing a semiconductor substrate by creating nanoasperities at a polishing interface between the polishing layer and the wafer during polishing by providing the high modulus phase component at the polishing interface, either as protrusions from the polishing layer, or by being released from the polishing layer into the polishing interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.