Method of forming a capacitor with high capacitance and low voltage coefficient
US6489196B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2002 |
| Grant date | Dec 3, 2002 |
| Priority date | — |
| Expiry date | Jan 28, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
Abstract
The present invention provides a method of forming a capacitor in an integrated circuit. The method comprises providing a semiconductor substrate having a conductive layer thereon. The partial conductive layer is removed to form an electrode. A plurality of first dopants are implanted on a surface of the electrode to form a first doped region. Then a plurality of second dopants are implanted into the electrode to form a second doped region below the first doped region. Then the capacitor is formed comprising the electrode. The first doped region and the second region can reduce voltage coefficient as well as increase capacitance of the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.