Capacitor fabrication process for analog flash memory devices
US6489200B1 · kind B1 · utility
4Cited by
11References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2000 |
| Grant date | Dec 3, 2002 |
| Priority date | — |
| Expiry date | Jul 11, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/022
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a capacitor on a substrate includes forming a first polysilicon layer overlying the substrate to define a floating gate. A second polysilicon overlying the first polysilicon layer is formed to define a control gate and a first electrode of the capacitor. A dielectric layer is formed over the second polysilicon layer. A third polysilicon layer is formed over the dielectric layer. The third polysilicon layer is etched to define a second electrode of the capacitor. Thereafter the dielectric layer is etched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.