Singulation method used in leadless packaging process
US6489218B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2001 |
| Grant date | Dec 3, 2002 |
| Priority date | — |
| Expiry date | Aug 14, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A singulation method comprising: (a) providing a molded product including semiconductor chips attached and electrically coupled to an upper surface of a lead frame wherein a lower surface of the lead frame is exposed from the bottom of the molded product, the lead frame including a plurality of units in an array arrangement and cutting streets between the units, each unit having a die pad and leads arranged at the periphery of the die pad, a first metal layer formed on the entire lower surface of the lead frame except the cutting streets; (b) etching the lower surface of the lead frame with the first metal layer as mask such that the cutting streets are etched away to form a plurality of grooves; and (c) cutting the etched molded product along the grooves to obtain the leadless semiconductor packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.