Clock synchronous semiconductor memory device allowing testing by low speed tester
US6489819B1 · kind B1 · utility
52Cited by
11References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 1998 |
| Grant date | Dec 3, 2002 |
| Priority date | — |
| Expiry date | Dec 6, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Pulses are generated using an edge of a clock signal applied from a low speed tester as a trigger, and internal clock signals are generated utilizing the pulses. Internal circuitry is operated in synchronization with the internal clock signals. Thus a synchronous semiconductor device operating at high speed can be tested using a low speed tester.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.