Segmented DAC calibration circuitry and methodology
US6489905B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2001 |
| Grant date | Dec 3, 2002 |
| Priority date | — |
| Expiry date | Aug 8, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/747
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A segmented digital-to-analog converter (DAC) has been described that uses a two-step calibration process to calibrate current sources to a single primary reference source. In one embodiment, the DAC includes sub-DACs, a reference generator circuit and a primary, or golden, reference source. Current sources of both the sub-DACs and the reference generator are calibrated to a golden current source or primary reference current. In one embodiment, the current sources each include a transistor coupled so that a gate voltage can be adjusted during calibration. The multiple current sources of the reference generator are first calibrated to the primary reference source. The calibrated output currents of the reference generator are then used to calibrate current sources in the sub-DACs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.