Multiple processors in a row for protocol acceleration
US6490631B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 1997 |
| Grant date | Dec 3, 2002 |
| Priority date | — |
| Expiry date | Aug 21, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/12
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A protocol accelerator includes a first processor connected to a host machine and programmed to provide a first protocol layer for data to be sent to a destination device. A second processor is connected to the first processor and is programmed to provide a second protocol layer for the data. A third processor is connected to the second processor and is programmed to provide a third protocol layer for the data. The third processor is connected to a network by which the data is sent to the destination device. The system can be configured for any number of protocol layers, by providing a dedicated processor in a pipelined configuration for each respective layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.