Scan structure for improving transition fault coverage and scan diagnostics
US6490702B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1999 |
| Grant date | Dec 3, 2002 |
| Priority date | — |
| Expiry date | Dec 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A scan chain latch circuit is provided. The scan chain latch circuit includes a first shift register latch and a second shift register latch. The scan chain latch circuit also includes a multiplexor connected between the first and second shift register latches, the multiplexor has a select line for controlling the function of the multiplexor. The multiplexor is configured for implementing an inverting mode such that a logic value may be passed via the multiplexor from the first shift register latch to the second shift register latch in one of a non-inverted state and an inverted state based upon the state of the select line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.