Packaging process for wafer level IC device
US6492196B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 7, 2002 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Jan 7, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The provision of a semiconductor wafer, which has been formed with a plurality of chips that each can be existent independently; the pre-cure process, in which the buffer layer has not been completely baked or hardened yet, but just for making the buffer layer be in stable condition; the pre-cut process, in which a cut is made at the position of the buffer layer corresponding to the boundary of each IC to make a gap exited between each two adjacent ICs without containing any buffer layer; the post-cut process, in which the buffer layer has completely baked and hardened; the singulation process, in which the both wafer and buffer layer are cut simultaneously to make the plural ICs separated from each other to become IC device that can act independently. Since the invention has processed pre-cut before the complete hardening, so when processing the complete bake, because there is pre-remaining space available for the buffer layer for thermal expansion, it can reduce the stress applied on the wafer to further keep the completeness of the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.