Utilization of macro power routing area for buffer insertion
US6492205B1 · kind B1 · utility
4Cited by
8References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2000 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Dec 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and a method for forming cells in power line areas between macro cell in a macro block area. In a power line level, a pin is formed between VSS and VDD lines. The pin is connected to the buffer cell. Next a signal line layer is formed and the signal line is connected to the pin and to a driver. In a first embodiment the driver is formed in a standard cell area. In a second embodiment the driver is formed in a micro cell. A signal line is connected to the pin and the driver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.