Louis Liu
12Patents
6h-index
17Co-inventors
63Inventor score
Filing activity: May 20, 1988 → Dec 3, 2009
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7494846B2 | Design techniques for stacking identical memory dies | Electricity | 27 | Active |
| US8365115B2 | System and method for performance modeling of integrated circuits | Physics | 23 | Active |
| US6668360B1 | Automatic integrated circuit design kit qualification service provided through the internet | Physics | 15 | Expired |
| US6583045B1 | Chip design with power rails under transistors | Electricity | 15 | Expired |
| US6818931B2 | Chip design with power rails under transistors | Electricity | 11 | Expired |
| US4933860A | Method for fabricating a radio frequency integrated circuit and product formed thereby | Electricity | 7 | Expired |
| US6492205B1 | Utilization of macro power routing area for buffer insertion | Electricity | 4 | Expired |
| US7853905B1 | Performing early DFT-aware prototyping of a design | Physics | 3 | Active |
| US6925614B2 | System and method for protecting and integrating silicon intellectual property (IP) in an integrated circuit (IC) | Physics | 2 | Expired |
| US8375347B2 | Driven metal critical dimension (CD) biasing | Physics | 2 | Active |
| US6855967B2 | Utilization of MACRO power routing area for buffer insertion | Electricity | 0 | Expired |
| US8286119B2 | Systematic method for variable layout shrink | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.