Method for novel SOI DRAM BICMOS NPN
US6492211B1 · kind B1 · utility
135Cited by
22References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2000 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Sep 7, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed herein a unique fabrication sequence and the structure of a vertical silicon on insulator (SOI) bipolar transistor integrated into a typical DRAM trench process sequence. A DRAM array utilizing an NFET allows for an integrated bipolar NPN sequence. Similarly, a vertical bipolar PNP device is implemented by changing the array transistor to a PFET. Particularly, a BICMOS device is fabricated in SOI. The bipolar emitter contacts and CMOS diffusion contacts are formed simultaneously of polysilicon plugs. The CMOS diffusion contact is the plug contact from bitline to storage node of a memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.