Method of forming a transistor with a strained channel
US6492216B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2002 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Feb 7, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
Abstract
A method of forming a tensile or compressive strained channel region for a semiconductor device, such as a MOSFET device, allowing improved carrier transport properties and increased device performance to be realized, has been developed. The method features the epitaxial growth of a semiconductor layer such as silicon, or silicon-germanium, with the incorporation of atoms such as carbon. The silicon-germanium-carbon channel layer, under biaxial tensile or compressive strain, is then overlaid with an optional silicon capping layer, used to accommodate the overlying, thermally grown silicon dioxide gate insulator layer, of the MOSFET device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.