Complementary metal gates and a process for implementation
US6492217B1 · kind B1 · utility
93Cited by
29References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 4, 2000 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Oct 4, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor device includes a gate dielectric overlying a substrate, a barrier layer overlying the gate dielectric, and a gate electrode overlying the barrier layer. The barrier layer of the device has a physical property that inhibits interaction between the gate dielectric and the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.