Method of making triple self-aligned split-gate non-volatile memory device

US6492231B2 · kind B2 · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Chun-Mai Liu · San Jose, US
• Kung-Yen Su · San Jose, US
• Kai-Man Chan · Sha Tin, CN
• Albert Kordesch · San Jose, US

Key dates

• Filing date: Jun 8, 2001
• Grant date: Dec 10, 2002
• Expiry date: Jun 8, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

A method for fabricating a triple self-aligned non-volatile memory device is disclosed. The method includes forming isolation oxide on a substrate. A plurality of floating gates are formed by depositing and self-aligning a first polysilicon layer to the isolation oxide. A common source area is then defined on the substrate between the floating gates. A second polysilicon layer is deposited over the common source area and self-aligned with respect to the isolation oxide. A third polysilicon layer is deposited adjacent to the plurality of floating gates. A plurality of select gates are then formed by self-aligning the third polysilicon layer to the isolation oxide. Furthermore, at least one drain area is defined on the substrate.