Integrated circuits and manufacturing methods

US6492282B1 · kind B1 · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Dirk Tobben · Fishkill, US
• Peter Weigand · Unterhaching, DE
• Matthias Ilg · Fishkill, US

Key dates

• Filing date: Apr 30, 1997
• Grant date: Dec 10, 2002
• Expiry date: Apr 30, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76837
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of filling gaps between adjacent gate electrodes of a semiconductor structure. A self-planarizing material is deposited over the structure. A first portion of such material flow between the gate electrode to fill the gaps and a second portion of such material becomes deposited over tops of the gate electrodes and over the gaps to form a layer with a substantially planar surface. A phosphorous dopant is formed in the second portion of the self-planarizing material. Thus, relatively small gaps may be filled effectively with a layer having a very planar surface for subsequent photolithography. The phosphorous dopant provides gettering to remove adverse effects of alkali contaminant ions which may enter the gap filling material. The dielectric constant of the material filing the gaps, i.e., the first portion of the gap filling material, being substantially free of such contaminants, has a relatively low dielectric constant thereby reducing electrical coupling between adjacent electrodes. The self-planarizing material is a flowable material. The flowable oxide may be spun on or may be deposited by gaseous deposition. The phosphorous dopant may be provided by, for example: impla…