Stacked semiconductor device and semiconductor system
US6492718B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 19, 2000 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Dec 19, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked semiconductor device includes a plurality of stacked wiring substrates each having connection electrodes and wires connected to the connection electrodes and each mounted with a semiconductor device, a plurality of conductive via boards each interposed between adjacent two wiring substrates and having an opening for enclosing the semiconductor device, an uppermost wiring substrate formed on the top of the stacked wiring substrates and having wires connected to the connection electrodes, and a lowermost wiring substrate formed under the stacked wiring substrates and having wires connected to the connection electrodes, wherein heat radiation/shield conductive layers are formed on the uppermost and lowermost wiring substrates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.