Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
US6492726B1 · kind B1 · utility
194Cited by
8References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2000 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Aug 3, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15312
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In accordance with the objectives of the invention a new package is provided that is provided with a cavity that is shaped such that more than one semiconductor device can in a vertical direction be mounted in the cavity of the package. The devices that are mounted inside the cavity of the package are separated by separate components of insulation, the overlying devices are electrically interconnected by horizontally positioned solder bumps and vertical interconnect plugs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.