Socket calibration method and apparatus
US6492797B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2000 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Feb 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R35/005
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus for calibrating tester timing accuracy during testing of integrated circuits. An ATE tester measures itself through reference blocks that have the same relevant dimensions as the integrated circuits to be tested. The number of reference blocks required is equal to the number of signal terminals on an integrated circuit to be tested being subject to timing calibration. A signal trace electrically connects a different signal terminal to a common reference terminal on each reference block. Each signal trace used should be closely matched both physically and electrically to the other signal traces used in the set of reference blocks, so that the electrical path length associated with each trace is nearly identical. To perform the timing calibration, the reference blocks may be mounted on a single fixture one at a time, or using multi-site fixtures, multiple reference blocks may be used in parallel. The fixture provides electrical connection of the reference block to the loadboard, and ultimately, the tester.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.