Power efficient and high performance flip-flop
US6492854B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2001 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Aug 30, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power efficient flip-flop includes a power switch regulating power supplied to a high speed latch in the flip-flop. When the power switch is activated, causing the high speed latch to receive power, the high speed latch captures data received by the flip-flop. The captured data is propagated by the high speed latch to the output of the flip-flop. Simultaneously, the high speed latch transmits the data to a low leakage latch connected to the high speed latch. Then, power is removed from the high speed latch, and the data retained in the low leakage static latch is now released to the output of the flip-flop. The power efficient flip-flop minimizes leakage current generated by the high speed latch by removing a path to ground when power is not provided to the high speed latch. A decoupling device is connected to the power switch to substantially eliminate a coupling effect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.