Synchronous latching bus arrangement for interfacing discrete and/or integrated modules in a digital system and associated method
US6493407B1 · kind B1 · utility
3Cited by
11References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1997 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Oct 1, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital bus arrangement and an associated method are disclosed. The bus arrangement includes an input synchronization layer and an output synchronization layer. Data transfer between the modules is synchronized using a master clock signal such that data originated by one module is latched and placed on the bus in one clock cycle. Thereafter, in a second or subsequent clock cycle, the data is synchronously latched at the other modules of the system such that the data is available to an intended module. No logic circuitry is present between the input and output synchronization layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.