Recovery from writeback stage event signal or micro-branch misprediction using instruction sequence number indexed state information table
US6493821B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 1998 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Jun 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipelined microprocessor is provided. The pipelined microprocessor includes a writeback stage which signals an event and sends a sequence number of an instruction which had the event. The event may be, for example, a fault, a trap or a branch misprediction. The pipelined microprocessor further includes a decode stage which stores recovering state information for respective instructions and is responsive to the writeback stage signaling the event by using the sequence number to access the stored information to retrieve recovery state information of the instruction which had the event. The recovery state information may include, for example, a pointer to a next linear instruction, a pointer to a branch target instruction, a branch prediction, or an instruction source. Event recovery micro-code determines a next instruction to execute using the recovery state information, the next instruction being executed after a machine recovery.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.