Integrated circuit design error detector for electrostatic discharge and latch-up applications

US6493850B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Puvvada Venugopal · Bengaluru, IN
• Snehamay Sinha · Dallas, US
• Sridhar Ramaswamy · Sunnyvale, US
• Charvaka Duvvury · Plano, US
• Guru Prasad · Austin, US
• C. S. Raghu · Scotch Plains, US
• Gopalaro Kadamati · Plano, US

Key dates

• Filing date: Feb 16, 2001
• Grant date: Dec 10, 2002
• Expiry date: Jun 1, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/367
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

For quantitatively identifying sensitivities against electrostatic discharge (ESD) and latch-up in an integrated circuit (IC) design (before the actual IC is fabricated), the disclosed computer system and method combine information from the design netlist, the elements model, a safe operating file, and a list of stress simulations, and apply a simulated, quantified ESD event to the design. The observed sensitivities of the design elements to ESD and latch-up are then quantitatively analyzed, critical stress values are judged, and element failures recorded. Finally, element and location lists of sensitivities and failures are output in a specific format.