Methods of forming high-k gate dielectrics and I/O gate oxides for advanced logic application
US6495422B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2001 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Nov 9, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of simultaneously forming a high-k metal oxide dielectric layer and a gate oxide dielectric layer comprising the following steps. A structure having isolation regions which separate the structure into at least one core device active region and one I/O active region is provided. A buffer layer is formed over the structure and the isolation regions. A metal containing layer is formed over the buffer layer. The metal containing layer and the buffer layer are patterned to: form an exposed patterned metal containing layer within the at least one core device action region; and expose the structure within the at least one I/O active region. The exposed patterned metal containing layer and the exposed structure within the at least one I/O active region are oxidized to simultaneously form: the high-k metal oxide dielectric layer within the at least one core device active region; and the gate oxide dielectric layer within the at least one I/O active region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.