Method to reduce capacitance for copper interconnect structures
US6495452B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 18, 1999 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Aug 18, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for creating a copper damascene structure, totally encapsulated with conductive barrier shapes, has been developed. After formation of a copper damascene structure, encased with tantalum or tantalum nitride barrier shapes, coating the bottom and sides of the copper damascene structure, another conductive barrier shape, is formed on the top surface of the copper damascene structure. This conductive barrier shape, located on the top surface of the copper damascene structure, is formed via patterning of a blanket conductive barrier layer, via an anisotropic RIE procedure, using a photoresist shape as an etch mask. The photoresist shape in turn, is formed in negative photoresist layer, using the same photolithographic exposure plate, previously used to define the opening in the insulator layer, in which the copper damascene structure resides. This combination results in a photoresist shape, directly overlying the portion of the conductive barrier layer that directly overlays the copper damascene structure, allowing a conductive barrier shape, to be formed only overlying the top surface of the copper damascene structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.