Field-effect transistor with multidielectric constant gate insulation layer
US6495890B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 2000 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Sep 8, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A field-effect transistor comprises a semiconductor substrate, a gate insulation film formed selectively on the semiconductor substrate, a gate electrode formed on the gate insulation film, source/drain regions formed in surface portions of the semiconductor substrate along mutually opposed side surfaces of the gate electrode, the source/drain regions having opposed end portions located immediately below the gate electrode, each of the opposed end portions having an overlapping region which overlaps the gate electrode, and a channel region formed in a surface portion of the semiconductor substrate, which is sandwiched between the opposed source/drain regions. That portion of the gate insulation film, which is located at the overlapping region where at least one of the source/drain regions overlaps the gate electrode, has a lower dielectric constant than that portion of the gate insulation film, which is located on the channel region. Thereby, a short channel effect can be fully suppressed, and a high-speed operation can be realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.