Scalable high frequency integrated circuit package
US6495911B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2000 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Aug 17, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and implementing system are described in which a tri-plate chip carrier is effective to significantly reduce electromagnetic signal radiation and provide enhanced noise immunity. The tri-plate structure includes a ground layer, a middle signal conducting layer upon which an integrated circuit is mounted, and a top reference potential layer. The middle layer includes groups of printed circuit conductors extending from the chip to the outer edges of the carrier. The top layer is arranged to have separate electrically isolated conducting areas for VDD and ground reference potential connections. The conducting areas are arranged such that each group of signal conductors in the middle signal layer has a ground potential area above it and a ground potential area below it to provide enhanced signal isolation and reduced electromagnetic radiation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.