Patent · US Expired

Protection circuit for an integrated circuit

US6496119B1 · kind B1 · utility

36Cited by

6References

16Claims

0Family size

Assignees

Infineon Technologies AG · DE
Siemens Aktiengesellschaft · DE

Inventors

Jan Otterstedt · Unterhaching, DE
Michael Richter · Ottobrunn, DE
Michael Smola · Munich, DE
Martin Eisele · Birkenfeld, DE

Key dates

Filing date	Sep 20, 2000
Grant date	Dec 17, 2002
Priority date	—
Expiry date	Sep 20, 2020

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The invention is directed to a protective circuit for an integrated circuit 1. This protective circuit is preferably arranged in a plurality of circuit levels 2, 3 under and/or above the intergrated circuit 1. It exhibits a plurality of interconnects 10, 11 that are charged with different signals of one or more signal generators. The different signals, after traversing the interconnects 10, 11, are analyzed with one or more detectors in that the signals received by detectors are respectively compared to rated reference signals, and an alarm signal is forwarded to the integrated circuit given the presence of a significant difference. On the basis of this alarm signal, the integrated circuit is switched into a security mode that makes an analysis or a manipulation of the integrated circuit practically impossible.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.