Wafer flattening process and storage medium
US6496748B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 21, 1999 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Jan 21, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/30625
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer flattening process designed to flatten the entire surface of the wafer including the outer rim of the wafer by inserting dummy data corresponding to the data of the outer rim of the wafer in the data of the outside of the wafer, and a storage medium for the same. An area S is set at an outside position exactly an etching radius r from an outer rim Wc of the wafer Wc ahd the nozzle relative speed at the position-speed data D of points P4-1 to P4-3 closest to an imaginary line L passing through the point P4 inside the area S near the outer rim Wc is set to be the same as the nozzle relative speed of the position-speed data D of the point P4. Due to this, the nozzle spraying the activated species gas G moves as if along the imaginary line L and the portion of the point P4 is etched flat by superposition of the activated species gas G of the nozzle passing through the points P4-1 to P4-3, the point P4, and the point P6.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.