Queue based memory controller
US6496906B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2001 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | May 5, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller for a computer memory which decodes memory requests into individual primitive memory operations which are then queued into separate operation queues. The operation queues independently issue their queued primitive memory operations to the memory in order to initiate the memory request. The operation queues monitor and adhere to timing and ordering dependencies between the primitive memory operations that are queued and those that have already been transmitted to the memory. Once a primitive memory operation is transmitted to the memory, it is dequeued from its respective operation queue. A control queue monitors the progress of the primitive memory operations transmitted to the memory, completes the initiated memory request and provides timing and ordering dependency data to the operation queues.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.