One mask solution for the integration of the thin film resistor
US6497824B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2000 |
| Grant date | Dec 24, 2002 |
| Priority date | — |
| Expiry date | Sep 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/474
Abstract
A method for integrating a thin film resistor (60) into an interconnect process flow. Metal interconnect lines (40) are formed over a semiconductor body (10). An interlevel dielectric (50) is then formed over the metal interconnect lines (40). Conductively filled vias (62) are then formed through the interlevel dielectric (50) to the metal interconnect lines (40). A thin film resistor (60) is then formed connecting between at least two of the conductively filled vias (62) using a single mask step. Connection to the resistor (60) is from below using a via process sequence already required for connecting between interconnect layers (40, 64). Thus, only one additional mask step is required to incorporate the resistor (60).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.