Method for implementing SOI transistor source connections using buried dual rail distribution
US6498057B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2002 |
| Grant date | Dec 24, 2002 |
| Priority date | — |
| Expiry date | Mar 7, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and silicon-on-Insulator (SOI) semiconductor structures are provided for implementing transistor source connections for SOI transistor devices using buried dual rall distribution. A SOI semiconductor structure Includes a SOI transistor having a silicide layer covering a SOI transistor source, a predefined burled conduction layer to be connected to a SOI transistor source, and an Intermediate conduction layer between the SOI transistor and the predefined buried conduction layer, A first hole for a transistor source connection to a local interconnect is anisotropically etched in the SOI semiconductor structure to the silcide layer covering the SOI transistor source. A second hole aligned with the local interconnect hole is anisotropically etched through the SOI semiconductor structure to the predefined buried conduction layer. An Insulator is disposed between the second hole and the intermediate conduction layer. A conductor Is deposited in the first and second holes to create a transistor source connection to the predefined burled conduction layer In the SOI semiconductor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.