John E. Sheets, II
151Patents
16h-index
50Co-inventors
89Inventor score
Filing activity: Feb 13, 1996 → May 10, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7227183B2 | Polysilicon conductor width measurement for 3-dimensional FETs | Electricity | 195 | Expired |
| US6121659A | Buried patterned conductor planes for semiconductor-on-insulator integrated circuit | Electricity | 83 | Expired |
| US6774734B2 | Ring oscillator circuit for EDRAM/DRAM performance monitoring | Physics | 60 | Expired |
| US7183780B2 | Electrical open/short contact alignment structure for active region vs. gate region | Electricity | 57 | Expired |
| US6492244B1 | Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices | Electricity | 42 | Expired |
| US5872697A | Integrated circuit having integral decoupling capacitor | Electricity | 33 | Expired |
| US5889306A | Bulk silicon voltage plane for SOI applications | Electricity | 28 | Expired |
| US6498057B1 | Method for implementing SOI transistor source connections using buried dual rail distribution | Electricity | 24 | Expired |
| US6429099B1 | Implementing contacts for bodies of semiconductor-on-insulator transistors | Emerging Cross-Sectional Technologies | 22 | Expired |
| US7009905B2 | Method and apparatus to reduce bias temperature instability (BTI) effects | Physics | 20 | Expired |
| US8525245B2 | eDRAM having dynamic retention and performance tradeoff | Electricity | 20 | Active |
| US6287901A | Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors | Electricity | 19 | Expired |
| US6667518B2 | Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices | Electricity | 18 | Expired |
| US6670716B2 | Silicon-on-insulator (SOI) semiconductor structure for implementing transistor source connections using buried dual rail distribution | Electricity | 17 | Expired |
| US9455313B1 | High-density integrated circuit via capacitor | Electricity | 17 | Active |
| US7241649B2 | FinFET body contact structure | Electricity | 16 | Expired |
| US6645796B2 | Method and semiconductor structure for implementing reach through buried interconnect for silicon-on-insulator (SOI) devices | Electricity | 16 | Expired |
| US8816470B2 | Independently voltage controlled volume of silicon on a silicon on insulator chip | Electricity | 15 | Active |
| US8549363B2 | Reliability and performance of a system-on-a-chip by predictive wear-out based activation of functional components | Physics | 15 | Active |
| US8492220B2 | Vertically stacked FETs with series bipolar junction transistor | Electricity | 12 | Active |
| US9024387B2 | FinFET with body contact | Electricity | 10 | Active |
| US10037792B1 | Optimizing data approximation analysis using low power circuitry | Physics | 10 | Active |
| US9916890B1 | Predicting data correlation using multivalued logical outputs in static random access memory (SRAM) storage cells | Physics | 10 | Active |
| US7727887B2 | Method for improved power distribution in a three dimensional vertical integrated circuit | Electricity | 10 | Active |
| US8754417B2 | Vertical stacking of field effect transistor structures for logic gates | Electricity | 10 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.