Redirecting I/O address holes
US6499074B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 1999 |
| Grant date | Dec 24, 2002 |
| Priority date | — |
| Expiry date | Aug 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4226
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor-oriented system, such as a microcontroller or computer system, supports a programmable address decoder used to redirect accesses to unassigned I/O address space. I/O accesses to unassigned addresses or address holes can be directed to multiple busses. If a programmable switch associated with the programmable address decoder is set to a first predetermined value, then certain I/O addresses are directed to a first bus. If the programmable switch associated with the programmable address decoder is set to a second predetermined value, then certain I/O addresses are directed to a second bus. If the first bus is coupled to PC/AT compatible peripheral devices and the second bus is coupled to non-PC/AT compatible devices, then the I/O address redirection capability selectively supports a PC/AT compatible mode or a non-PC/AT compatible mode. Certain integrated devices coupled to the second bus can be bypassed or disabled as desired to allow redirection of I/O to external devices coupled to the first bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.