Distributed interface for parallel testing of multiple devices using a single tester channel
US6499121B1 · kind B1 · utility
106Cited by
37References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 1, 1999 |
| Grant date | Dec 24, 2002 |
| Priority date | — |
| Expiry date | Mar 1, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/16225
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for testing a number of integrated circuit (IC) devices under test (DUTs) having interface circuitry coupled to a single or multi-channel tester for receiving data values from the tester and providing error information concerning the DUTs. The interface circuitry forwards data values (received from the tester over a single channel) to a number of DUTs in parallel. The circuitry performs comparisons using data values read from the DUTs, and in response generates error values indicative of the comparison. The error values may then be returned to the tester over the same or a different channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.