Method and apparatus for debugging an integrated circuit
US6499123B1 · kind B1 · utility
172Cited by
50References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2000 |
| Grant date | Dec 24, 2002 |
| Priority date | — |
| Expiry date | Apr 12, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8053
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having a normal mode for operating under normal operating conditions and a debug mode for operating to test and debug the integrated circuit. The integrated circuit includes a plurality of output pins that carry a first plurality of signals in the normal mode and carry a second plurality of signals in the debug mode. In one embodiment, the integrated circuit embodies a microprocessor. The microprocessor may include logic circuitry for enabling the second plurality of signals to be output from a multiplexer to the output pins in response to a predetermined event, such as a hit in an associated memory unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.